In semiconductor device fabrication, the various processing steps fall into four general categories: deposition, removal, patterning, and modification of electrical properties. Deposition is any process that grows, coats, or otherwise transfers a material onto the wafer. Available technologies consist of physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE) and more recently, atomic layer deposition (ALD) among others. Removal processes are any that remove material from the wafer either in bulk or selective form and consist primarily of etch processes, both wet etching and dry etching such as reactive ion etch (RIE). Chemical-mechanical planarization (CMP) is also a removal process used between levels. Patterning covers the series of processes that shape or alter the existing shape of the deposited materials and is generally referred to as lithography. For example, in conventional lithography, the wafer is coated with a chemical called a “photoresist.” The photoresist is exposed by a “stepper,” a machine that focuses, aligns, and moves the mask, exposing select portions of the wafer to short wavelength light. The unexposed regions are washed away by a developer solution. After etching or other processing, the remaining photoresist may be removed by plasma ashing.
Modification of electrical properties has historically consisted of doping transistor sources and drains, originally by diffusion furnaces and later by ion implantation. These doping processes are followed by furnace anneal, or in advanced devices, by rapid thermal anneal (RTA), which serve to activate the implanted dopants. Modification of electrical properties now also extends to reduction of dielectric constant in low-k insulating materials via exposure to ultraviolet light in UV processing (UVP).
Many modern chips have eight or more levels produced in over 300 sequenced processing steps. The raw wafer is engineered by at minimum, growth of an ultra-pure, defect-free silicon surface through epitaxy. In the most advanced logic devices, prior to silicon epitaxy, tricks are performed to improve the performance of the transistors to be built. One method involves introducing a “straining step” wherein a silicon variant such as “silicon-germanium” (SiGe) is deposited. Once the epitaxial silicon is deposited, the crystal lattice becomes stretched somewhat, resulting in improved electronic mobility. Another method, called “silicon on insulator” technology involves the insertion of an insulating layer between the raw silicon wafer and the thin layer of subsequent silicon epitaxy. This method results in the creation of more idealized transistors with minimized parasitic effects.
Front end surface engineering is followed by: growth of the gate dielectric, traditionally silicon dioxide (SiO2), patterning of the gate, patterning of the source and drain regions, and subsequent implantation or diffusion of dopants to obtain the desired complimentary electrical properties. In memory devices, storage cells (conventionally capacitors) are also fabricated at this time, either into the silicon surface or stacked above the transistor.
Once the various semiconductor devices have been created, they must be interconnected to form the desired electrical circuits. This process involves creating metal interconnecting wires that are isolated by insulating materials often referred to in the industry as dielectrics. The insulating material was traditionally a form of SiO2 or a silicate glass, but recently new low dielectric constant materials are being used. These dielectrics presently have dielectric constants around 2.7, although materials with constants as low as 2.2 are being offered to chipmakers.
Historically, the metal wires consisted of aluminum. In this approach to wiring often called “subtractive aluminum,” blanket films of aluminum are deposited first, patterned, and then etched, leaving isolated wires. Dielectric material is then deposited over the exposed wires. The various metal layers are interconnected by etching holes, called “vias,” in the insulating material and depositing tungsten in them with a chemical vapor deposition (CVD) technique. This approach is still used in the fabrication of many memory chips such as dynamic random access memory (DRAM) as the number of interconnect levels is small, currently no more than four.
More recently, as the number of interconnect levels for logic has substantially increased due to the large number of transistors that are now interconnected in a modern microprocessor, the timing delay in the wiring has become significant prompting a change in wiring material from aluminum to copper and from the aforementioned silicon dioxides to newer low-K materials. This performance enhancement also comes at a reduced cost via “damascene” processing that eliminates processing steps. In damascene processing, in contrast to subtractive aluminum technology, the dielectric material is deposited first as a blanket film and is patterned and etched leaving holes or trenches. In “single damascene” processing, copper is then deposited in the holes or trenches surrounded by a thin barrier film resulting in filled vias or wire “lines” respectively. In “dual damascene” technology, both the trench and via are fabricated before the deposition of copper resulting in formation of both the via and line simultaneously, further reducing the number of processing steps. The thin barrier film, called Copper Barrier Seed (CBS), is a necessary evil to prevent copper diffusion into the dielectric. As the presence of excessive barrier film competes with the available copper wire cross section, formation of the thinnest yet continuous barrier represents one of the greatest ongoing challenges in copper processing.
Design Rule Checking or Check(s) (DRC) is the area of Electronic Design Automation that determines whether a particular chip design satisfies a series of recommended parameters called Design Rules. Design rule checking is a major step during Physical verification of the design, which may also involve LVS (Layout versus schematic) Checks, XOR Checks, ERC (Electrical Rule Check) and Antenna Checks.
Design Rules are a series of parameters provided by semiconductor manufacturers that enable the designer to verify the correctness of his or her schematic and/or mask set. Design rules are specific to a particular semiconductor manufacturing process. A design rule set specifies certain geometric and connectivity restrictions to ensure sufficient margins to account for variability in semiconductor manufacturing processes, so as to ensure that most of the parts work correctly. Design rule sets have become increasingly more complex with each subsequent generation of semiconductor process.
The main objective of DRC is to achieve a high overall yield and reliability for the design. If design rules are violated the design may not be functional. To meet this goal of improving die yields, DRC has evolved from simple measurement and Boolean checks, to more involved rules that modify existing features, insert new features, and check the entire design for process limitations such as layer density. A completed layout consists not only of the geometric representation of the design, but also data that provide support for manufacture of the design. While design rule checks do not validate that the design will operate correctly, they are constructed to verify that the structure meets the process constraints for a given design type and process technology.
DRC software usually takes as input a layout in a standard format, and produces a report of design rule violations that the designer may or may not choose to correct. Carefully “stretching” or waiving certain design rules is often used to increase performance and component density at the expense of yield.
DRC is a very computationally intense task. If run on a single CPU, customers may have to wait up to a week to get the result of a Design Rule check for modern designs. Most design companies require DRC to run in less than a day to achieve reasonable cycle times since the DRC will likely be run several times prior to design completion. Some examples of DRC's in IC design include but are not limited to the following:                a) active to active spacing        b) well to well spacing        c) minimum channel length of the transistor        d) minimum metal width        e) metal to metal spacing metal fill density (for processes using CMP)        f) ESD and I/O rules        
Meeting a set of design rules may not be adequate wherein the rules may be affected by the complexity of the layout pattern containing a particular feature or rule. A particular rule may be adequate in one pattern but require modification in another pattern to insure that a particular IC layout has the best manufacturability.
Therefore, there is a need for a method to augment standard DRC specifically targeting problematic layouts using 2D pattern matching and enforcing different design rules. This will ensure that designs that pass checking will indeed be manufacturable.